Ni or Co silicides are commonly used in CMOS technology to form metallic contacts with silicon. Typically, the Ni or Co layer is applied to the silicon substrate using high vacuum physical vapor deposition (PVD) processes such as sputtering or evaporation. While these processes are highly precise, the cost associated with them is prohibitive for several other applications that need silicide contact layers such as MEM devices, and silicon photovoltaic applications.
One alternative to high vacuum physical vapor deposition processes is to apply Ni or Co using solution processes, such as in electroless deposition or electrodeposition of Ni or Co. In this approach, however, it is difficult to control the silicide formation because the adhesion of metals deposited from solution processes on semiconductors is marginal. This is a problem because the delamination of metal films from the semiconductor surface prevents a uniform formation of silicide during thermal annealing. Traditionally, the annealing process in CMOS technology converts the whole metal layer deposited by PVD processes into silicide. Therefore, the silicide thickness is controlled by controlling the thickness of the metal layer deposited by PVD. In solution processes, however, it is very difficult to deposit a very thin, uniform layer of metal films on a semiconductor surface due to the low nucleation density of most of these methods. Therefore, to better control the silicide formation, a layer of Ni or Co from a solution-based process is deposited on silicon samples with sufficient thickness to ensure continuous metal coverage. The samples are then annealed to form a layer of silicide (while leaving unreacted Ni or Co metal on the surface). Unreacted Ni or Co is then removed by selective chemical etching to prevent delamination of the metal and the silicide. The added steps required to control the silicide formation in the solution-based processes complicate the device manufacturing.